triple pll field programmable vcxo clock synthesizer ics270 mds 270 b 1 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com triple pll field programmable vcxo clock synthesizer preliminary information description the ics270 field programmable vcxo clock synthesizer generates up to eight high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency crystal input. it is designed to replace crystal s and crystal oscillators in most electronic systems. using ics? versaclock tm software to configure plls and outputs, the ics270 contains a one-time programmable (otp) rom for field programmability. programming features include vcxo, eight selectable configuration registers and up to two sets of four low-skew outputs. using phase-locked loop (pll) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. it can replace vcxos, multiple crystals and oscillators, saving board space and cost. the ics270 is also available in factory programmed custom versions for high-volume applications. features ? packaged as 20-pin tssop ? eight addressable registers ? replaces multiple cr ystals and oscillators ? output frequencies up to 200 mhz at 3.3 v ? input crystal frequency of 5 to 27 mhz ? up to eight reference outputs ? up to two sets of four low-skew outputs ? operating voltages of 3.3 v ? controllable outp ut drive levels ? advanced, low-power cmos process ? available in pb (lead) free packaging block diagram voltage controlled crystal oscillator gnd 2 3 vdd pdts pll2 pll3 divide logic and output enable control s2:s0 clk1 clk8 clk7 clk6 clk5 clk4 clk3 clk2 3 otp rom with pll values x2 crystal external capacitors are required. x1 pll1 vin idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 1 data sheet ics270
idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 2 ics270 triple pll field programmable vcxo clock synthesizer tsd triple pll field programmable vcxo clock mds 270 b 2 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics270 preliminary information pin assignment pin descriptions 13 4 12 5 11 vdd 8 9 10 gnd clk3 clk7 clk1 clk4 clk8 17 16 clk5 3 s1 vin s2 18 pdts 1 x1 s0 vdd 20 x2 19 14 2 7 gnd clk2 vdd clk6 15 6 20 pin (173 mil) tssop pin number pin name pin type pin description 1vininput voltage input to vcxo. zero to 3.3 v signal which controls the vcxo frequency 2 s0 input select pin 0. internal pull-up resistor. 3 s1 input select pin 1. internal pull-up resistor. 4vddpower connect to +3.3 v. 5 clk1 output output clock 1. weak internal pull-down when tri-state. 6 clk2 output output clock 2. weak internal pull-down when tri-state. 7 clk3 output output clock 3. weak internal pull-down when tri-state. 8 clk4 output output clock 4. weak internal pull-down when tri-state. 9 gnd power connect to ground. 10 x1 xi crystal input. connect this pin to a crystal. 11 x2 xo crystal output. connect this pin to a crystal. 12 vdd power connect to +3.3 v. 13 clk5 output output clock 5. weak internal pull-down when tri-state. 14 clk6 output output clock 6. weak internal pull-down when tri-state. 15 clk7 output output clock 7. weak internal pull-down when tri-state. 16 clk8 output output clock 8. weak internal pull-down when tri-state. 17 gnd power connect to ground. 18 pdts input power-down tri-state. powers down enti re chip and tri-states clock outputs when low. internal pull-up resistor. 19 vdd power connect to +3.3 v. 20 s2 input select pin 2. internal pull-up resistor.
idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 3 ics270 triple pll field programmable vcxo clock synthesizer tsd triple pll field programmable vcxo clock mds 270 b 3 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics270 preliminary information external components the ics270 requires a minimum number of external components for proper operation. series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . decoupling capacitors as with any high-performance mixed-signal ic, the ics270 must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias on the decoupling circuit. quartz crystal the ics270 vcxo function consists of the external crystal and the integrated vcxo oscillator circuit. to assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. the frequency of oscillation of a quartz crystal is determined by its ?cut? and by the load capacitors connected to it. the ics270 incorporates on-chip variable load capacitors that ?pull? (change) the frequency of the crystal. the crystal specified for use with the ics270 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pf. recommended crystal parameters: initial accuracy at 25 c 20 ppm temperature stability 30 ppm aging 20 ppm load capacitance 14 pf shunt capacitance, c0 7 pf max c0/c1 ratio 250 max equivalent series resistance 35 ? max the external crystal must be connected as close to the chip as possible and should be on the same side of the pcb as the ics270. there should be no via?s between the crystal pins and the x1 and x2 device pins. there should be no signal traces underneath or close to the crystal. see application note man05. crystal tuning load capacitors the crystal traces should include pads for small fixed capacitors, one between x1 and ground, and another between x2 and ground. stuffing of these capacitors on the pcb is optional. the need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by pcb layout. the typical required capacitor value is 1 to 4 pf. to determine the need for and value of the crystal adjustment capacitors, you will need a pc board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, cl. to determine the value of the crystal capacitors: 1. connect vdd of the ics270 to 3.3 v. connect pin 1 of the ics270 to the second power supply. adjust the voltage on pin 1 to 0v. measure and record the frequency of the clk output. 2. adjust the voltage on pin 1 to 3.3 v. measure and record the frequency of the same output. to calculate the centering error: where: f target = nominal crystal frequency error 10 6 x f 3.0v f tet arg ? () f 0v f tet arg ? () + f tet arg ---------------------------------------------------------------------- - error xtal ? =
idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 4 ics270 triple pll field programmable vcxo clock synthesizer tsd triple pll field programmable vcxo clock mds 270 b 4 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics270 preliminary information error xtal =actual initial accuracy (in ppm) of the crystal being measured if the centering error is less than 25 ppm, no adjustment is needed. if the centering error is more than 25ppm negative, the pc board has excessive stray capacitance and a new pcb layout should be considered to reduce stray capacitance. (alternately, the crystal may be re-specified to a higher load capacitance. contact ics for details.) if the centering error is more than 25 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. the value for each of these caps (in pf) is given by: external capacitor = 2 x (centering error)/(trim sensitivity) trim sensitivity is a parame ter which can be supplied by your crystal vendor. if you do not know the value, assume it is 30 ppm/pf. after any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than 25 ppm). ics270 configuration capabilities the architecture of the ics270 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. the frequency multiplier pll provides a high degree of precision. the m/n values (t he multiplier/divide values available to generate the target vco frequency) can be set within the range of m = 1 to 1024 and n = 1 to 32,895. the ics270 also provides separate output divide values, from 2 through 63, to allow the two output clock banks to support widely differing frequency values from the same pll. each output frequency can be represented as: output drive control the ics270 has two output drive settings. low drive should be selected when outputs are less than 100 mhz. high drive should be selected when outputs are greater than 100 mhz. (consult the ac electrical characteristics for output rise and fall times for each drive option.) ics versaclock software ics applies years of pll optimization experience into a user friendly software that accepts the user?s target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. the user does not need to have prior pll experience or determine the optimal vco frequency to support multiple output frequencies. versaclock software quickly evaluates accessible vco frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. the user may evaluate output accuracy, performance trade-off scenarios in seconds. absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics270. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. outputfreq reffreq m n ---- - ? = parameter condition min. typ. max. units supply voltage, vdd referenced to gnd 7 v inputs referenced to gnd -0.5 vdd+0.5 v clock outputs referenced to gnd -0.5 vdd+0.5 v
triple pll field programmable vcxo clock mds 270 b 5 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics270 preliminary information recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c storage temperature -65 150 c soldering temperature max 10 seconds 260 c junction temperature 125 c parameter min. typ. max. units ambient operating temperature (ics270pg/pglf) 0 +70 c ambient operating temperature (ics270pgi/pgilf) -40 +85 c power supply voltage (measured in respect to gnd) +3.135 +3.3 +3.465 v power supply ramp time 4 ms reference crystal parameters refer to page 3 parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 3.465 v operating supply current input high voltage idd config. dependent - see versaclock tm estimates ma eight 33.3333 mhz outs, pdts = 1, no load, note 1 27 ma pdts = 0, no load, note 1 500 a input high voltage v ih s2:s0 vdd/2+1 v input low voltage v il s2:s0 0.4 v input high voltage, pdts v ih vdd-0.5 v input low voltage, pdts v il 0.4 v input high voltage v ih iclk vdd/2+1 v input low voltage v il iclk vdd/2-1 v output high voltage (cmos high) v oh i oh = -4 ma vdd-0.4 v output high voltage v oh i oh = -8 ma (low drive); i oh = -12 ma (high drive) 2.4 v output low voltage v ol i ol = 8 ma (low drive); i ol = 12 ma (high drive) 0.4 v short circuit current i os low drive 40 ma high drive 70 nom. output impedance z o 20 ? parameter condition min. typ. max. units idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 5 ics270 triple pll field programmable vcxo clock synthesizer tsd
idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 6 ics270 triple pll field programmable vcxo clock synthesizer tsd triple pll field programmable vcxo clock mds 270 b 6 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics270 preliminary information note 1: example with 25 mhz crystal input with eight outputs of 33.3 mhz, no load, and vdd = 3.3 v. ac electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c note 1: external crystal device must conform with pullable crystal specifications listed on page 3. note 2: measured with 15 pf load. note 3: duty cycle is configuration dependent. most configurations are min 45% / max 55%. thermal characteristics internal pull-up resistor r pus s2:s0, pdts 190 k ? internal pull-down resistor r pd clk outputs 220 k ? input capacitance c in inputs 4 pf parameter symbol conditions min. typ. max. units input frequency f in fundamental crystal 5 27 mhz output frequency 0.314 200 mhz crystal pullability f p 0v< vin < 3.3 v, note 1 100 ppm vcxo gain vin = vdd/2 + 1 v, note 1 110 ppm/v output rise/fall time t of 80% to 20%, high drive, note 2 1.0 ns output rise/fall time t of 80% to 20%, low drive, note 2 2.0 ns duty cycle note 3 40 49-51 60 % power-up time pll lock-time from power-up 410ms pdts goes high until stable clk output 0.6 2 ms one sigma clock period jitter configuration dependent 50 ps maximum absolute jitter t ja deviation from mean, configuration dependent + 200 ps pin-to-pin skew low skew outputs -250 250 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 93 c/w ja 1 m/s air flow 78 c/w ja 3 m/s air flow 65 c/w thermal resistance junction to case jc 20 c/w parameter symbol conditions min. typ. max. units
ics270 triple pll field programmable vcxo clock synthesizer tsd triple pll field programmable vcxo clock mds 270 b 7 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics270 preliminary information marking diagrams markin g diagrams (pb free) notes: 1. ###### is the lot number. 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?i? denotes industrial temperature range (if applicable). 4. ?l? denotes pb (lead) free package. 5. bottom marking: country of origin. 1 10 11 20 270pg ###### yyww 1 10 11 20 270pgi ###### yyww 1 10 11 20 270pgl ###### yyww 1 10 11 20 270pgil ###### yyww idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 7
idt? / ics? triple pll field programmable vcxo clock synthesizer ics270 8 ics270 triple pll field programmable vcxo clock synthesizer tsd triple pll field programmable vcxo clock mds 270 b 8 revision 040705 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics270 preliminary information package outline and package dimensions (20-pin tssop, 173 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" su ffix to the part number are the pb-fr ee configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. versaclock tm is a trademark of integrated circuit systems, inc. all rights reserved. part / order number marking shipping packaging package temperature ics270pg see page 7 tubes 20-pin tssop 0 to +70 c ics270pgi tubes 20-pin tssop -40 to +85 c ics270pglf tubes 20-pin tssop 0 to +70 c ics270pgilf tubes 20-pin tssop -40 to +85 c index area 1 2 24 d e1 e seating plane a1 a a2 e - c - b .10 (.004) c c l millimeters inches symbol min max min max a ? 1.20 ? .047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 6.40 6.60 0.252 0.260 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.450.75.018.030 0 8 0 8
ics270 triple pll field programmable vcxo clock synthesizer tsd ics9148-53 frequency generator & integrated buffers for mother boards tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com sd0060cn02270t 60.00 mhz differential delay line for commercial applications tsd
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